Optimize Parity Encoding for Power Reduction in Content Addressable Memory Journal title: International Journal of Engineering Sciences & Research Technology Authors: Nisha Sharma Subject(s):
AN EFFICIENT ARCHITECTURE FOR DE-BLOCKING FILTER Journal title: ICTACT Journal on Microelectronics Authors: Meghavi H. Modi, Nehal N. Shah Subject(s):
SIMULATED ANNEALING ALGORITHM FOR MODERN VLSI FLOORPLANNING PROBLEM Journal title: ICTACT Journal on Microelectronics Authors: Jenifer J, Anand S, Levingstan Y Subject(s):
VHDL implementation of a Novel Low Power Squaring Circuit Using YTVY Algorithm of Vedic Mathematics Journal title: International journal of Emerging Trends in Science and Technology Authors: Pabitra Kumar Mohapatra Subject(s):
Implementation of Fault Tolerant FIR Filter for Digital Communication Systems Journal title: GRD Journal for Engineering Authors: Jyotishma Bharti, Tarana Afrin Chandel Subject(s):
Design of Low Power Transversal FIR Filter For VLSI Signal Processing Applications Journal title: International journal of Emerging Trends in Science and Technology Authors: Soumee Sharmeela Pattnaik Subject(s):
A Broad Review on Various VLSI CAD Algorithms for Circuit Partitioning Problems Journal title: International Journal of Mechanical and Production Engineering Research and Development (IJMPERD ) Authors: R. MANIKANDAN, K. R. SEKAR, K. HARIHARAN Subject(s):
VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm Journal title: Journal of ICT Research and Applications Authors: Rachmad Vidya Wicaksana Putra, Trio Adiono Subject(s):
Design and Simulation of a New Optimized Full-Adder Using Carbon Nano Tube Technology Journal title: روش های هوشمند در صنعت برق Authors: Abbas Asadi Aghbolaghi, Mehran Emadi Subject(s):
Dynamic Power reduction of synchronous digital design by using of efficient clock gating technique Journal title: International Journal of Engineering and Techniques Authors: Subject(s):
