16 BIT UNSIGNED MULTIPLIER USING PROPOSED CSLA
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 5
Abstract
This project deals with the comparison of the VLSI design of the conventional carry select adder (CSLA) based 16-bit unsigned integer multiplier and the VLSI design of the proposed carry select adder (CSLA) based 16-bit unsigned integer multiplier. Both the VLSI design of multiplier multiplies two 16-bit unsigned integer values and gives a product term of 32-bit Values. The Conventional CSLA based multiplier uses the delay time of 12.845ns for performing multiplication operation where as in proposed CSLA Based multiplier also uses nearly the same delay time for multiplication operation. But the area needed for CLAA multiplier is reduced to 30 % by the CSLA based multiplier to complete the multiplication operation. These multipliers are implemented using Xilinx 14.5.
Authors and Affiliations
Praveen B S, Manjunanth Badiger
Keywords
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