A Lossless Secret Image Sharing Scheme based on Pixel Partitioning
Journal Title: International Journal of Electronics Communication and Computer Technology - Year 2012, Vol 2, Issue 1
Abstract
Secret sharing method divides a secret into some components called shadow images where each shadow image looks meaningless. Based on this idea, we propose a simple secret image sharing scheme in this article. This scheme is based on bitwise operations. We have used matrix addition and subtraction processes for share generation and reconstruction processes respectively. This technique allows a secret image to be divided as n image shares so that all n image shares have to be used to reconstruct the secret image and any (n ? 1) or fewer image shares cannot get sufficient information to reveal the secret image. The proposed scheme has no pixel expansion and can reconstruct the secret image precisely. It is an effective, reliable, and secure method to prevent the secret image from being lost, stolen or corrupted. Experimental results prove that the proposed scheme is efficient because of strong security and accuracy.
Authors and Affiliations
Tapasi Bhattacharjee| Dept. of Information Technology Techno India Kolkata, India tapasi.dgp@gmail.com, Jyoti Prakash Singh| Dept. of Information Technology National Institute of Technology Patna, India jps@nitp.ac.in, Amitava Nag| Dept. of Information Technology Academy of Technology Hooghly, India amitava.nag@ieee.or
Artifacts Correction in MRI Imaging Using RF Pulse Phase Modulation and Recurrence Solving
Currently MRI is extensively used in medical analysis to produce high-eminence images for its a variety of useful features, such as high-resolution potential, subjective anatomic cross-sectional image, and high tissue...
Double Stacked Gates MOSFET Technology In both Planar as well as 3D Gate(Finfet) MOSFET’s
This paper describes the performance of a planar mosfet as well as the performance of finfet mosfet when dual gate layers are used on the same side of the mosfet channel with separate gate oxide layers, thus providing...
On Usability Relationships of Computer Technology Input Artifacts and Rural Development in India
Computer Technology is going to penetrate deep into all areas of development, but easy-to-use interface availability for rural chunk is a big challenge. Regular PC interface with a keyboard is definitely deplorable by ma...
Design and Implementation of 64-Bit Execute Stage for VLIW Processor Architecture on FPGA
FPGA implementation of 64-bit execute unit for VLIW processor, and improve power representation have been done in this paper. VHDL is used to modelled this architecture. VLIW stands for Very Long Instruction Word. This P...
Efficient Implementation of Low Density Parity Check (LDPC) Decoder In VLSI
The best error-correcting performance can be achieved by using non-binary low-density parity check (NB-LDPC) codes. This can be of reduced decoding complexity with high cost efficiency and is mostly preferable than binar...