A Reconfigurable Less Power Asynchronous FPGA Design with Power Gating and Level encoding dual rail technique
Journal Title: International Journal of Science Engineering and Advance Technology - Year 2014, Vol 2, Issue 11
Abstract
The implementation of a low power logic based asynchronous circuit with the help of power gated logic. In asynchronous power gated logic (APL) circuit, each pipeline stage was incorporated with efficient charge recovery logic (ECRL) gate; handshake controller and partial charge reuse (PCR) mechanism. The main objective was, to provide a new lower power solutions using power gating (PG) for very large scale integration (VLSI) designers. ECRL have the simplest structure and high energy efficiency which was used to implement the functional blocks of APL circuit. PG adopts two approaches, fine grain and coarse grain approach. The circuit based asynchronous with fine grain approach is called asynchronous fine grain power gated logic (AFPL) circuit and coarse grain approach is said to be asynchronous coarse grain power gated logic (ACPL) circuit. In the PCR mechanism, part of the charge on the output node of an ECRL gate was reused to charge the output node of another ECRL gate. This help to reducing the energy dissipation. Therefore, leakage power reduction should begin with power gated logic and PCR mechanism. To mitigate the area overhead of the AFPL circuit, coarse grain power gating technique have been developed.
Authors and Affiliations
Mr. K. Raghuram M. Tech. (Ph. D)| Assoc. Prof. , Dept. Of ECE, Pragati Engineering College, JNTUK, India, raghuram_kantipudi@hotmail.com, Ms. Dhana Lakshmi Yarkareddy| PG Scholar, Dept. Of ECE, Pragati Engineering College, JNTUK, India, lakshmibtech21@gmail.com
Keywords
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