An Fpga Implementation Of N/N+1 Prescaler For A Low Power Single Phase Clock Distribution System
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2014, Vol 3, Issue 10
Abstract
In the VLSI design clock distribution in an IC is very important as it deals with 70% of the power consumption. This paper deals with the design of prescaler to reduce the power consumption by the clock. A prescaler is used to reduce a high frequency electrical signal to a low frequency by integer division. Demand for low power circuits increased in conjunction with a higher level of integration. A multiband flexible divider is used to reduce the power consumption. The proposed design consists of a wideband multimodulous prescaler which divides the input frequency. Two flip-flops and different logic gates are embedded between the flip-flops to achieve two ratios and also to reduce the switching power and short circuit power in the prescaler. Prescalers are typically used at very high frequency to extend the upper frequency range of frequency counters, phase locked loop (PLL) synthesizers, and other counting circuits. The design doesn’t require any extra flip-flop, thus saving a considerable amount of power. Reduction of power consumption and delay is very important for high speed low power applications. The proposed prescaler based approach reduces the area and power significantly. A 32/33 prescaler, 47/48 prescaler along with a multimodulous 32/33/47/48 prescaler which incorporates the proposed 2/3prescaler are designed and implemented. The proposed system can be simulated using Modelsim for logical verification, Xilinx ISE tool for synthesizing and the Verilog language is used.
Authors and Affiliations
V Satya Deepthi, Sneha Suprakash, USBK MahaLakshmi
Keywords
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