Analysis of Efficient Adiabatic Logic Circuits and Their Power Extraction in Finfet (10nm) and Comparison With 90nm and 45nm
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2017, Vol 5, Issue 5
Abstract
This paper describes the design style and analysis of low power adiabatic logic circuits based on ECRL (Efficient Charge Recovery Logic Circuits), PFAL(Positive Feedback Adiabatic Logic) and SCRL(Split Charge Recovery Logic).These logic families always functions based on four phase power clock. These designs have the proficiency of energy saving by recycling or reusing the certain amount of the energy, which helps in reduction of power dissipation. This paper describes how the power and delay factor depends on the timing analysis. “CADENCE” virtuoso has used for the design of energy saving adiabatic circuit. In the analysis, three nanometer technologies have compared. This paper shows that how the power and delay vary as the frequency is increased. In the analysis, ECRL, PFAL and SCRL technologies also have compared. It has found that adiabatic circuits are superior for low power applications.
Authors and Affiliations
Sunnivesh Suman, M. Murali Krishna, I. Sreenivasa Rao
Keywords
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- EP ID EP24311
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