Area Efficient Carry Select Adder (AE-CSLA) using Cadence Tools
Journal Title: INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY - Year 2014, Vol 10, Issue 10
Abstract
To perform fast addition operation, CSLA is one of the fastest adders used in many data-processing processors. Analyzing the structure of Regular CSLA (R-CSLA) and Modified CSLA (M-CSLA), there is a scope to reduce the area further. This work uses a simple gate level modification and a modified XOR gate is proposed to be used in the circuit. Based on this modification, 16-bit Area Efficient CSLA (AE-CSLA) is designed which provides 32% reduction in area when compared with R-CSLA and 12.5% reduction in area when compared with M-CSLA. This work is implemented in CADENCE VIRTUOSO using 180nm CMOS process technology.
Authors and Affiliations
Gagandeep Singh , Chakshu Goel
Keywords
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