Comparative Study of Various Binary Floating Point Multiplier Techniques Using VHDL
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2016, Vol 4, Issue 4
Abstract
In computing, floating point describes a method of representing an approximation of a real number in a way that can support a wide range of values. Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. However, area and speed are usually conflicting constraints so that improving speed results mostly in larger area in implementation of the system. This project presents study of various binary floating point multiplier techniques using various Algorithms of an IEEE 754 single precision floating point multiplier targeted for Altera. Now a days there is a scope of advance technology in which the design of more efficient multiplier is dominant part of digital system. This objective of this study is to find algorithm which offers higher speed and low power consumption. Subsequently, tradeoffs between area and delay parameters for each multiplier design are also analyzed for the different schemes. This approach is well-suited for several complex and portable VLSI circuits. In this work, the comparative study of Booth multiplier, Dadda multiplier, Wallace Tree multiplier are carried out by analyzing area, power and delay characteristics with particular importance on low power consumption.
Authors and Affiliations
Rupali Umekar, Dr. Vasif Ahmed
Keywords
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