Design and Implementation for Multi-Level Cell Flash Memory Storage Systems
Journal Title: International Journal of Advanced Computer Science & Applications - Year 2011, Vol 2, Issue 11
Abstract
The flash memory management functions of write coalescing, space management, logical-to-physical mapping, wear leveling, and garbage collection require significant on-going computation and data movement. MLC flash memory also introduces new challenges: (1) Pages in a block must be written sequentially. (2) Information to indicate a page being obsolete cannot be recorded in its spare area. This paper designs an MLC Flash Translation Layer (MFTL) for flash-memory storage systems which takes new constraints of MLC flash memory and access behaviors of file system into consideration. A series of trace driven simulations is conducted to evaluate the performance of the proposed scheme. Our experiment results show that the proposed MFTL outperforms other related works in terms of the number of extra page writes, the number of total block erasures, and the memory requirement for the management.
Authors and Affiliations
Amarnath Gaini , K Vijayalaxmi , Sathish Mothe
Keywords
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