Design of Power Efficient and High Speed Carry Select Look Ahead Adder Using SP-D3l Logic
Journal Title: The International Journal of Technological Exploration and Learning - Year 2013, Vol 2, Issue 5
Abstract
Minimizing area and power is the most challenging task in modern VLSI design. Adders are the most extensively used components in many integrated circuits; the design of power efficient high-speed data path logic systems forms the largest areas of research in VLSI system design. This paper presents a new vibrant logic named sp-D3L that conquers the speed limitations of D3L. Power consumption is considerably reduced by using the sp-D3L logic. Carry Select Look Ahead Adder is one of the fastest adders used in many data-processing circuits to perform fast arithmetic and logical functions. The simulation results show that there is reduction in the area and power consumption by using the sp-D3L logic.
Authors and Affiliations
K. Priyameenakshi| Assistant Professor, ECE Centre for Advanced research, Muthayammal Engg College Namakkal, India, K. Bashkaran| Assistant Professor, ECE Centre for Advanced research, Muthayammal Engg College Namakkal, India
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- EP ID EP8493
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