Fault Recovery Using Scan Chain Based Approach Technique
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 2
Abstract
Recent applications of all embedded system will get failure due to multiple faults occurring in the system. This fault should be detected and corrected simultaneously while running the system. In practise we use a scan chain based Triple modular redundancy (TMR) approach technique. It is very expensive and requires three times more hardware resources. This paper explores the application of reduced-precision redundancy (RPR) to the problem, the metric used to evaluate the effectiveness of RPR is the bit error rate (BER) achieved by the FPGA. RPR is applied to a real FPGAbased system and is validated with extensive fault injection experiments. These method can be achieved by using reduced scan chain based multiple fault error recovery (RSCMFER) method.
Authors and Affiliations
M. Sridevi, Ms. D. Devi
Keywords
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