Functional Verification of Enhanced RISC Processor
Journal Title: Indian Journal of Computer Science and Engineering - Year 2013, Vol 4, Issue 5
Abstract
This paper presents design and verification of a 32-bit enhanced RISC processor core having floating point computations integrated within the core, has been designed to reduce the cost and complexity. The designed 3 stage pipelined 32-bit RISC processor is based on the ARM7 processor architecture with single precision floating point multiplier, floating point adder/subtractor for floating point operations and 32 x 32 booths multiplier added to the integer core of ARM7. The binary representation of the floating point numbers employed in the design eliminates the need for floating point registers and uses same set of registers thereby reducing the complexity, area and cost. Mask based data reversal barrel shifter performs parallel flag computations during shift or rotate and has least worst case delay of 0.94 ns compared to other barrel shifters. The hardware of the 32-bit RISC processor core has been modeled in Verilog HDL, simulated in VCS. Verification of a complex design such as 32-bit RISC is one of the major challenges as it consumes more time. In this work, a verification environment is being developed to verify the design RISC processor core.
Authors and Affiliations
SHANKER NILANGI , SOWMYA L
Keywords
Related Articles
- EP ID EP162122
- DOI -
- Views 111
- Downloads 0
Mutant Generation for Aspect Oriented Programs
Testing of aspect oriented programs is a new programming paradigm. Many researchers had contributed their research in the field of testing AOP. Mutation testing is an emerging area of research in testing of aspect orient...
INTEGRATION OF ICT AND E-GOVERNANCE IN RAJASTHAN
IT (Information Technology) is a term which is basically used to actions and technologies allied with the use of computer and communication resources. It was treated as an electronic technique to storage, retrieval and p...
ZONE WISE ANALYSIS OF CAVITATION IN PRESSURE DROP DEVICES OF PROTOTYPE FAST BREEDER REACTOR BY KURTOSIS BASED RECURRENT NETWORK
This paper aims to analyze the quality of pressure drop devices (orifices), which is used for flow zoning in proto type fast breeder reactor (PFBR) by analyzing the occurrence of cavitation. The magnitude of root mean sq...
ENTROPY CORRELATION COEFFICIENT TECHNIQUE FOR VISUAL DATA IN MULTIMEDIA SENSOR NETWORK
The nodes are interconnected in Wireless multimedia sensor networks (WMSNs) in the form of wireless mode. These interconnected devices transmit their locally processed data to the sink. With the availability of low cost...
Efficient Resource Scheduling in Data Centers using MRIS
Scheduling the resources is decisive in shared data centers. Today scheduling algorithms focus only on onedimensional resource models, infact the multiple resources (e.g. Memory, Storage, CPU and Network bandwidth) can b...