High Performance MAC Unit for FFT Implementation
Journal Title: International Journal of Modern Engineering Research (IJMER) - Year 2014, Vol 4, Issue 1
Abstract
In this paper we have proposed an efficient way of implementing a Fast Fourier Transform (FFT) processor using high performance pipelined Multiply and Accumulate (MAC) unit. The multiplication unit is implemented using Modified Radix 4 Booth Multiplier algorithm. The proposed multiplier circuits are based on the modified Booth algorithm and the pipeline technique which are the most widely used to accelerate the multiplication speed. The adder unit is implemented using an area efficient Carry Select Adder (AECSA). As a result we can achieve lower area as compared with that of a normal Carry Select Look ahead Adder (CLSA). The implementation is done using Verilog HDL code. The simulation of the over all design is carried out using NC launch. The synthesis of our design is done using RTL compiler in Cadence. Analysis of the synthesis report shows the design to be of high performance and to be area optimised.
Authors and Affiliations
Tinju Tresa
Keywords
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- EP ID EP115615
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