High Speed Noise Tolerant Domino Circuit For Wide Fan-in AND-OR Gates
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 5
Abstract
In this paper, a new technique is proposed for wide fan-in OR gates. Here the current comparison based domino circuit is used to design a low leakage, high speed wide fan-in circuit. Dynamic gates have been excellent choices in the design of high performance modules in modern microprocessors. Dynamic gates are indispensable for constructing wide high-speed OR and AND–OR gates in CMOS. They are especially useful in multiport memories, where single- ended read bit-lines are needed for compactness and (even) low-power consumption. Circuits implemented with dynamic logic have very low parasitic capacitance and the number of transistors required in this technique is very less compared to static CMOS logic. This wide fan-in OR gates are simulated using 14nm high performance predictive technology model demonstrate 60% power reduction and at least 2.41× noise-immunity improvement at the same delay compared to the standard domino circuits for 256-bit OR gates.
Authors and Affiliations
K. Rajasri, M. Manikandan
Keywords
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- EP ID EP20375
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