https://journals.indexcopernicus.com/representative/article/create?issueId=Utilizaton of Wallace Tree Multiplier in the Design of Scalable Microprogrammed Fir Filter Architectures
Journal Title: International Journal of engineering Research and Applications - Year 2017, Vol 7, Issue 8
Abstract
Field programmable gate array (FPGA) is widely used for efficient hardware realization of digital signal processing (DSP) circuits and systems. FPGAs have emerged as a platform of choice for faster and efficient realization of computer-intensive applications. Finite impulse response (FIR) filter is the core of any DSP and communication system To improve the performance of FIR filter, an efficient multiplier is required..Wallace multiplier used in this project for the implementation of sequential and parallel microprogrammed FIR filter architectures.The designs are realized using Xilinx Spartan-6 FPGA. Tools used: Xilinx ISE 14.1, Spartan-6 FPGA.
Authors and Affiliations
P. Koteswara Rao, Md. Shabeena Begum, Ch. Siva Rajesh
Keywords
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