Implementation of a Fast Binary Floating Point Dadda Multiplier
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 11
Abstract
This project presents a high speed binary floating point multiplier based on Dadda Algorithm. To improve speed multiplication of mantissa is done using Dadda multiplier replacing Carry Save Multiplier. The design achieves high speed with maximum frequency of 526 MHz compared to existing floating point multipliers. The floating point multiplier is developed to handle the underflow and overflow cases. To give more precision, rounding is not implemented for mantissa multiplication. The multiplier is implemented using Verilog HDL and it is targeted for Xilinx Virtex-5 FPGA. The multiplier is compared with Xilinx floating point multiplier core.
Authors and Affiliations
Thalari Mohan, G. Mukesh
Keywords
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