Implementation of NoC on FPGA with Area and Power Optimization
Journal Title: EAI Endorsed Transactions on Context-aware Systems and Applications - Year 2019, Vol 6, Issue 16
Abstract
On-chip bus-based communication has many shortcomings to it, including resource sharing, delay, latency and cost (power and area). Network on Chip (NoC) is an innovation that is planned to eliminate the shortcomings to buses such as compact systems, size, speed, power and area. The goal of working was to design a usable and researchable general-purpose 2x2 mesh NoC architecture, which is not application specific, and have optimized area and power. Desired NoC was coded and deployed on FPGA Spartan-3 kit in a generic mode, with the efficient area and power utilization than traditional deployments.
Authors and Affiliations
Momil Ijaz, Huma Urooj, Muhammad Athar Javed Sethi
Keywords
Related Articles
- EP ID EP45816
- DOI http://dx.doi.org/10.4108/eai.23-5-2019.158953
- Views 281
- Downloads 0
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