Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2014, Vol 3, Issue 9
Abstract
Radio communication exhibits the highest energy consumption in wireless sensor nodes. The sensor networks are intended to support a variety of applications . Providing sensor network with flexible nodes design will make possible to support a variety of application . In these paper we currently they are designed around off the shelf low power microcontrollers, But by employing a more appropriate processing element , the energy consumption can be significantly reduced. This paper describes the design and implementation of newly proposed folded – tree architecture for on – the node data processing in wireless sensor networks using Berunt – kung Parallel prefix operation and data locality in hardware . Due to Berunt – Kung parallel prefix architecture it reduces the number of logic cells and delay is more . This paper is implemented and simulated in Xilinx ISE software and resulted are observed . Limited data set by pre – processing with parallel –prefix operations, reuseability with floding technique .
Authors and Affiliations
Kamanuru Naga Dasaradha, Putha Pavankumar Reddy
Keywords
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