Area and Power Efficient Modulo 2^n+1 Multiplier
Journal Title: International Journal of Modern Engineering Research (IJMER) - Year 2013, Vol 3, Issue 3
Abstract
Abstract: In this paper area-power efficient modulo 2n+1 multiplier is proposed. The result and one operand for the new modulo multipliers use weighted representation, while the other uses the diminished- 1. By using the radix-4 Booth recoding, the new multipliers reduce the number of the partial products to n/2 for even and (n+1)/2 for odd except for one correctionterm. According to our algorithm, the resulting partial products are added through inverted end around carry save adderinto two operands, which are finally adder by a 2-stage n-bit adder containing 2:1 multiplexer. By using the purposed adder,the new multipliers reduce the area and power. The analytical and experimental result indicates that the new modulo 2n+1 multipliers, offer reduced power and more compact area among all the existing structures.
Authors and Affiliations
K. Pitambar Patra
Keywords
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- EP ID EP151432
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