Comparitive Study Of Diffrent Multiplier Architectures
Journal Title: INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY - Year 2013, Vol 4, Issue 10
Abstract
This paper presents a comparative analysis of three different multiplier architectures. The three multipliers architecture are array multiplier, a column bypass multiplier, and a array multiplier using Reversal Logic schemes. The multipliers are implemented on Spartan 6 FPGA. The architectures are compared in terms of critical path delay, power dissipation and area. The different multipliers are compared in terms of dynamic power consumption due to the scaling effects on leakage current. Each of the three multipliers has its own trade-offs between power and delay
Authors and Affiliations
Prashant Kumar Sahu, Prof. Nitin Meena
Keywords
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