Design of Multiplier Less 32 Tap FIR Filter using VHDL
Journal Title: International Journal of Modern Engineering Research (IJMER) - Year 2014, Vol 4, Issue 6
Abstract
This Paper provide the principles of Distributed Arithmetic, and introduce it into the FIR filters design, and then presents a 32-Tap FIR low-pass filter using Distributed Arithmetic, which save considerable MAC blocks to decrease the circuit scale and pipeline structure is also used to increase the system speed. The implementation of FIR filters on FPGA based on traditional method costs considerable hardware resources, which goes against the decrease of circuit scale and the increase of system speed. It is very well known that the FIR filter consists of Delay elements, Multipliers and Adders. Because of usage of Multipliers in early design gives rise to 2 demerits that are: (i) Increase in Area and (ii) Increase in the Delay which ultimately results in low performance (Less speed). So the Distributed Arithmetic for FIR Filter design and Implementation is provided in this work to solve this problem. Distributed Arithmetic structure is used to increase the recourse usage and pipeline structure is used to increase the system speed. Distributed Arithmetic can save considerable hardware resources through using LUT to take the place of MAC units
Authors and Affiliations
Abul Fazal Reyas Sarwar1 , Saifur Rahman2
Keywords
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