OPTIMIZATION OF POWER USING CLOCK GATING
Journal Title: GRD Journal for Engineering - Year 2016, Vol 1, Issue 0
Abstract
Clock gating is one among the most widespread circuit technique to scale back power consumption. Clock gating is sometimes done at the register transfer level (RTL).Automatic synthesis of clock gating in gate level has been less explored, however it's certainly additional convenient to designers. Clock gating consists of 2 steps: extraction of gating conditions by merging gating conditions of individual flip-flops, implementation of the gating conditions with minimum quantity of further gates. In this paper, they show a way to do factored form matching, within which gating operates in factored kinds are matched, as way as possible, with factored kinds of the mathematician functions of existing combinable nodes within the circuit; further gates are then introduced, however just for the portion of gating functions that don't seem to be matched. Sturdy matching identifies matches that are explicitly gift within the factored forms, and their matching seeks matches that are inexplicit to the logic and so are tougher to get. Gate-level clock gating starts with a net list, with partial or no gating applied; some flip-flops are then selected for further gating to reduce the circuit’s power consumption, and a gating logic of the smallest possible size must then be synthesized.
Authors and Affiliations
D. Nirosha, T. Thangam
Keywords
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