Providing a fault-tolerant algorithm for on-chip interconnection networks
Journal Title: International Research Journal of Applied and Basic Sciences - Year 2013, Vol 4, Issue 7
Abstract
As technology scales, fault tolerance has become a key concern in the on-chip communication. On-chip network reliability can be increased with the development of fault-tolerant routing algorithms. Distributed routing algorithms are a class of algorithms in which routing decisions, taken without the knowledge of total network status. Given the time and placeevents of soft and permanent errors in system and on-chips, dynamic routing algorithms can adapt themselves in network on chip (NOC) required to the practical applications according to that. In this paper, a new dynamic routing algorithm (routing algorithm with error detection) for NOC practical programs that have capabilities to deal with failures for static and dynamic routing and detecting them from hardware errors will be presented. Also, our proposed algorithm was compared with some distributed routing algorithms, whose goals wereto maximize fault tolerance. This proposed dynamic routing algorithm can adapt itself in the network on chip (NOC) is required for practical applications. Finally, the simulation results of our proposed method were compared with several other algorithms.
Authors and Affiliations
Shahram Jamali| Department of Computer Engineering, Mohaghegh Ardabili University, Ardabil, Iran, Fateme Sarkohakiand| Department of Computer Engineering, Germi branch, Islamic Azad University, Germi, Iran, Reza Fotohi| Department of Computer Engineering, Germi branch, Islamic Azad University, Germi, Iran, Fotohi.Reza@Gmail.com
Keywords
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- EP ID EP5524
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