Reducing Leakage Power and Optimize the Area of Flip Flop Design using Stack Transistor Technique
Journal Title: International Journal of Innovation in Science and Mathematics - Year 2018, Vol 6, Issue 3
Abstract
In this paper, a low leakage power and area optimize CMOS logic is design and simulated without giving up its performance. The methodology is base on series connected MOSFET called as stack transistor technique. Abstractly, the reduce size series connected MOS transistor with gate terminal is connected with each other behaves line a single gate input transistor. In this paper, a CMOS layout is design and simulated in a deep submicron technology with significant reductions in power, leakage, and area of the hybrid circuits when compared with the conventional design.
Authors and Affiliations
Richa Singh, et al.
Keywords
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