Relaiblity and Fault Analysis in On-Chip Network
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2017, Vol 5, Issue 3
Abstract
System on chips towards multicore design for taking advantage of technology scaling and also for speeding up system performance through increased parallelism in the fact that power wall limits the increase of the clock frequency. Network on chip are shown to be feasible and easy to scale for supporting the large number of processing elements rather than point to point interconnect wire or shared buses. As industry moves towards many core chips, network on chips (NOCs) are emerging at the scalable fabric for interconnecting the cores. With power now the first –order design constraint, early-stage estimation of NOC power has been crucially important.
Authors and Affiliations
Ramalakshmi R, Tharani. B, Hari Priyadharshini S, Ilakkya S, Kanimozhi S
Keywords
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- EP ID EP23679
- DOI http://doi.org/10.22214/ijraset.2017.3217
- Views 280
- Downloads 5
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