Reliability Analysis of Nanoscale CMOS Device with HCI Effect
Journal Title: International Journal of Advanced Research in Computer Engineering & Technology(IJARCET) - Year 2013, Vol 2, Issue 9
Abstract
The paper focuses on the reliability due to hot carrier effects of CMOS and the HC effect under high gate voltage stress. How these stress factors vary with operating conditions, the required foundry qualification test data, and how to alter circuit topologies and device geometries to mitigate their effect are discussed .also where device reliability stress is high, a matter of serious concern is how many devices are being operated under such conditions. As the number of devices operated under high stress.
Authors and Affiliations
Sandeep lalawat, Prof. Y. S. Thakur
Keywords
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