slugEfficient Design of Power and Clock network for Large Chip Design Using Energy Recycling Technique
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2014, Vol 2, Issue 4
Abstract
This project aim is to develop a low- skew in multigiga hertz clocks circuit in operation with giant digital chips. A capacitance are often charged from the availability then discharged to ground. In giant digital chips quantity of wastage in electrical condenser is high owing to range of connections. Hence we are able to use associate energy use idea to cut back the general power consumption. By this energy use the wastage energy is employed by the opposite a part of the chip. For this energy use integrated clock driver and device network square measure incorporated. With exploitation of multigiga hertz the reduced size obtained within the inductance and electrical condenser while not loss and forty second of energy saving can occur. This idea is enforced by the 180nm cadence tool. We are able to additionally use clock buffer for ordered circuits.
Authors and Affiliations
Saravanakumar, Shafiq Mansoor, Rajarajan, Sumitha
Keywords
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