Design and Implementation of IEEE-754 Addition and Subtraction for Floating Point Arithmetic Logic Unit Journal title: International Journal of Advanced Research in Computer Engineering & Technology(IJARCET) Authors: V.VINAY CHAMKUR , Under the guidance of Chetana.R Subject(s):
FPGA Design of Pipelined 32-bit Floating Point Multiplier Journal title: International Journal of Computational Engineering and Management IJCEM Authors: Shaifal, Sakshi Subject(s):
