High Performance 6-Stage MIPS RISC Pipelined Processor Architecture Design
Journal Title: International Journal of engineering Research and Applications - Year 2019, Vol 9, Issue 1
Abstract
Pipelining is a process of concurrent execution of instructions in sections overlapped for effective utilization of resources. In this paper, high performance 64 bit, 6 stage MIPS RISC processor is designed to enhance the speed and for better handling of the criticality of the pipelining process. The paper consists of several optimizing devices and methods which not only concentrate on low power and high speed but also curtail the hazards in a critical manner. In the comparison study, our proposed architecture has reduced power by 19% and enhanced speed by 12%, when compared to our nearest counterpart. The simulation results are carried out with Xilinx platform and proved the superiority of our model. The 3-D graphic representation employed through MATLAB tool.
Authors and Affiliations
P. Indira, M. Kamaraju
Keywords
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- EP ID EP441062
- DOI 10.9790/9622- 0901011723.
- Views 156
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