Performance Investigation of Two-Stage Operational Amplifier
Journal Title: International Journal of Advanced Research in Computer Engineering & Technology(IJARCET) - Year 2013, Vol 2, Issue 7
Abstract
As CMOS technology scaling down transistor channel lengths to satisfy the thrust of low power consumption in modern electronics system . There is need to investigate the performance of the upcoming scaled channel length CMOS devices. At lower technology nodes mixed signal issues increases significantly this limits the performance of devices. In this paper two stage op-amp at different technology nodes of CMOS is designed and its performance has been investigated .CMOS technology nodes 16nm , 22nm ,32nm are used for evaluating the performance of two stage op-amp. Effect of temperature variations has been observed on two stage op-amp at 32nm CMOS technology
Authors and Affiliations
C. K. Kalawade , S. A. Shaikh
Keywords
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